Applications such as Systems On Chip (SoCs) or Application-Specific Integrated Circuits (ASICs) frequently use a function for mapping of the addresses of a memory to carry out a conversion from a logical-address space addresses to a physical-address space.
For example, specific applications may desire a predetermined logical-address space, such as logical rows and columns, which are defined during specification of the block. However, the physical-address space may be different on account of limitations during design of the chip layout. These may, for example, be limitations on the ratio between the width and the height of the memory, which is one of the significant factors during definition of the “floorplan” of the integrated circuit to enable determination of the total area of the integrated circuit.
To enable a re-use of one and the same block in various different applications, it is hence useful to develop a generic digital block (also referred to frequently as “Intellectual Property core” or “IP core”), which comprises a standard memory interface. In this case, an additional block is used, which is responsible for conversion of the logical addresses into real physical addresses.
For instance, a possible sphere of application can be a small drive unit for a display, where the drive unit has the task of reading the video data from a RAM for driving the respective pixels of the display. However, the ratio between the width and the height of the memory and of the display are not usually correlated. For example, the display may have a size of 220×176 pixels, while the memory has a size of 480×82. This is also highlighted in FIG. 1, which shows an example of mapping of a row R in the logical-address space LAS in a respective portion P into the physical-address space PAS.
In general, to enable a read and/or write access, the conversion block translates the logical address into the physical address of the memory with the following mathematical relations:
                              q          ⁡                      (                          x              ,              y                        )                          =                  quotient          ⁡                      (                                                            y                  ·                                      k                    1                                                  +                x                                            k                2                                      )                                              (        1        )                                          r          ⁡                      (                          x              ,              y                        )                          =                  remainder          ⁡                      (                                                            y                  ·                                      k                    1                                                  +                x                                            k                2                                      )                                              (        2        )            where k1 is the number of the (logical) columns of the display, k2 is the number of the (physical) columns of the RAM, (x,y) is the location on the display (i.e., the logical address), and (q, r) is the location in the memory (i.e., the physical address), where q is the quotient, and r is the remainder of the division.
The mathematical relation hence represents conversion from the two-dimensional space (x,y) into the two-dimensional space (q, r), i.e., translation of the logical space into the physical space. In general, the constants k1 and k2 can be any integer being greater than two.
FIG. 2 shows a block diagram of an example of possible implementation of Eqs. (1) and (2). In particular, provided in this implementation are a multiplier 102 and an adder 104 that compute the relation (y·k1+x). The result of the addition is sent to a block 106, for example a divider, which yields the quotient q and the remainder r of the division (y·k1+x)/k2.
This circuit thus enables conversion of logical address by specifying the parameters k1 and k2. This approach presents significant disadvantages in terms of performance (for example, in terms of maximum delay) and occupation of area of silicon, however.
It is likewise noted that, in some particular cases, it is possible to exploit the properties of the constant k1 and k2 to optimize the operations of multiplication and/or division at the bit level. For example, if the value of k1 and/or k2 is a multiple of 2, the operations of multiplication and/or division can be implemented via a simple shift operation. In particular cases, this behaviour can be exploited for implementing a dedicated “wrapper”, i.e., a combinational circuit, for example implemented within an ASIC, which enables direct conversion of a logical address into a physical address.
This is possible if there exists a simple relation between the constant k1 and k2 (for example, when k1 is a multiple of k2). However, in general these optimizations are not possible and, to speed up the circuit, there frequently remains the use of a structure of the pipeline type, which calls for a complex control structure and hence additional area of silicon.